This invention relates generally to improved apparatus and methods for implementing data processing operations in a data processing system, and particularly those data processing operations involving error checking and correction. Modern day data processing systems are typically implemented using integrated circuit (IC) chips. One of the problems presented by the use of IC chips is that the outputs provided by an IC chip are often limited in number and/or may have special restrictions with regard to their use. Gate array IC chips often are limited in this manner. For example, an IC chip might provide for 48 data inputs while providing a maximum of only 28 outputs. Furthermore, some of these outputs may be restricted, such as with regard to power handling capability.
When an IC chip provides an insufficient number of outputs, one possible solution is to employ two IC chips in a manner such that the required number of outputs are obtained by combining outputs from both IC chips. However, this use of two IC chips can have the disadvantageous result of requiring that the two IC chips have different designs because of differences in the functions they are to perform in response to the inputs applied thereto. This would typically be the case, for example, for error checking and correcting operations. It will be appreciated that increasing the number of differently designed IC chips which have to be provided can have a significant impact on the cost and complexity of the overall system.
One way of avoiding having to provide two differently designed chips where they perform differently is to include on each IC chip the capability of performing the functions required by both IC chips, the particular function to be performed by each IC chip in the system then being selected by applying a control signal to selection logic provided on the chip. However, the use of such an approach can significantly add to the cost and complexity of each such IC chip and could not in any event be employed for an IC chip which does not have sufficient logic to provide both functions.